Abstract-This materials with high carrier mobility and downscaled short

 

 

Abstract-This
paper presents a new analytical model of 2D Poisson equation to represent the
boundary condition, physical values and the electrical properties of the Organic
Field Effect Transistor (OFET). The parabolic approximation technique is used
to solve the 2D Poisson equation for preserves a close link to know about the
physical parameters of the device. The proposed method mainly focus on the
development of organic materials with high carrier mobility and downscaled
short channel devices to achieve high output current with fast switching speed.
I.
INTRODUCTION                Organic Field Effect Transistor is the recent area of
science and technology that aims the electronic devices based on organic
materials. It is attractive due to it fabrication process, flexible substrate
and a wide range of applications such as RFID tags, bendable displays and smart
cards. OFET circuit integration over large area and the metal contacts are
formed before deposition of the Organic Semiconducting (OSC) layer. Surface
modifications of metal contacts with thiol Self Assembled Monolayer (SAM) can
be used for obtaining low resistive and good quality semiconductor films on the
top of the source to drain electrodes for higher performance and better
uniformity of the electrical characteristics. One of the most important
parameters of the OFET is contact resistance (RC), which can limit the charge
carrier mobility and switching speed of the device. The contact resistance has
two main resistive components: (1) a component from the unavoidable charge
injection barrier at the metal-organic interface and (2) the bias dependent
component, which models the carrier transport through the amorphous organic
layer to the conducting channel between the drain and source electrodes. The
charge mobility in an OS is temperature dependent and carrier-concentration
dependent. This dependency is due to the charge transport mechanism in organic
semiconductors, which is the thermally assisted hopping of carriers between the
localized molecular states.This
paper is divided into six sections. Section II presents the related works
regarding the mobility and characteristics of the charge carriers. In section
III, background information regarding the proposed 2D Poisson equation and
analytical model presented in section IV. The proposed structural functions are
presented in Section V. Section VI contains the conclusion.II.
RELATED WORKS                Transconductance and the thickness of the organic
materials mentioned by Anu Assis 1 and Shaul Hameed et al. 3. According to
Fransiska, threshold voltage is derived depending on the density of charge
traps that can be used to know about the performance of the charge particle
movements in the threshold region. Hamidreza et al. 4 presented contact
resistance in the staggered organic field effect transistor and current
crowding mechanism for determine the gate bias conditions and the potential and
concentration of the accumulated charges in the active layer.   III.
METHODOLOGY                The carrier mobility of charges during their
transport through the high-density accumulation layer at the semiconductor
dielectric interface is evaluated in this method. Gate
dielectric is another component in OFET because it serves as a barrier between the
charge carriers transporting at the semiconductor-dielectric interface.A.     
Device StructureThe
patterned source/drain can be deposited above to the organic semiconductor and
the scaling of the channel length may depends on the effect of contact. A new
structure named Source-Gated Transistor (SGT) is formed when a barrier at the
source is used to restrict the current.  Under
normal operation, at low drain bias, the source barrier is reverse biased and
the semiconductor is depleted of carriers across its whole thickness, leading
to saturation of output current. This allows energy-efficient operation while
maintaining high intrinsic gain, from lower drain voltages than conventional
FETs. The figure shows that the gate used in this work Ti/Au on which the gate
dielectric material (PDI-8CN2) deposited with a thickness of 200nm.
Over that, pentacene the organic semiconductor with a thickness  of 50nm placed with gold electrodes for
source and drain contacts. The channel length and width were 200nm and 600nm
respectively. The bottom layer gate contact is with the thickness of 10nm
Ti/100nm Au. The variation in the characteristics of the OFET with the
thickness of the dielectric layer was studied by using the MATLAB software.

Fig.1
Device structure for OFETThe result of the
current control method, drain current is virtually independent of source-drain
separation, which increases performance uniformly in high-throughput
technologies with low-resolution patterning. The source gated transistor
structure was normally realized in inverted staggered structure, and would also
possible to be made in staggered structure.B.     
Gate Dielectric                Variation in dielectric layer thickness has a
profound influence in performance of OFETs and reducing the dielectric
thickness results in improvement in the current and mobility of the device. The
following table shows the value for the different dielectric material. And the
interface at the dielectric/semiconductor has profound influence on the
morphological formation of the semiconductor film and the charge transport
along the  channel.

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Table1.Polymer
gate dielectric used for OFETs. By applying varies dielectric material to the
organic semiconductor we can know the different behavior of the OFET.C.     
Analytical model An analytical model was developed
by considering the effect of trap states at the grain boundaries of the organic
semiconductor layer.                The
gate consist of two materials M1 and M2 with gate lengths L1 and L2 with two
different work function

 and

. Based on the positive or negative
potential applied to the gate terminal, the device behaves as n type OFET and p
type OFET respectively. Increasing positive voltage on the gate narrows the
energy barrier between the source and intrinsic region. The electrons tunnel
from the valence band of the p-doped source to the conduction band in the
intrinsic body and then move towards the n-doped drain by drift diffusion.                The
potential profile in the vertical direction is assumed to be a second-order
polynomial,   

Where,

The boundary conditions
in the channel region are: (a)Electric flux at the front-oxide gate interface
is continuous for OFET and Electric flux at the back gate-oxide

        

  (b) The back channel interface is continuous
for both the material  

 

 (c) The potential at the source and drain end.                The electric-field distribution along the channel
length can be obtained by differentiating the surface potential.

Where Vbi is
the built in potential, Eg is Band gap energy, q is elementary
charge, VGS is Gate to Source Voltage, VDS is Drain to
Source voltage ,

 is
relative permittivity of silicon and ,

 is
relative permittivity of silicon dioxide. These are the parameters used in the
analytical model equation. The potential of the metal 1 and metal 2 is given as

 

 

The
electric-field distribution along the channel length can be obtained by
differentiating the surface potential. The values of C11, C12,
C21, C22 can be determined by solving  the above equation 8 and 9 . Potential  

 and

 under
M1 and M2 can be obtained by solving the Poisson’s equation (3.1) using
boundary conditions (3.7), (3.8) and (3.9), therefore,

 

  The
gate work function of metal1 (

 is 4eV and metal2

 is 4.6eV. ? is the electron affinity. The coefficients of A, B,
C and D can be expressed as

 

 

 

Electric Field                The electric field distribution along the channel can
be obtained by differentiating the surface potential

The
vertical electric field can be written as

Drain currentThe mechanism of
flow of current IDS in OFET is based on Band-to-Band
Tunneling
of electrons from the valence band of the source to the conduction band of
channel region. Therefore, 

Then the value for the
G(E) is given as

Eg is the energy
band gap. The parameters used for MATLAB simulation are A=8.1×1017eV1/2/cm.s.V2
and B= 3.057×107V/cm-(eV)3/2.   IV RESULT AND DISCUSSION                In
this section , describe results of applying the proposed work of OFET using
parabolic abstraction method. The variation of the vertical electric field for
metal 1 with the channel length results are obtained y MATLAB simulation.

Fig : Variation
of vertical electric field as a function of the position along with channel at
metal 1.                At metal 2 the vertical electric
field changes according to the channel length then there is momentous change in
the potential. The rise within the electric field close to the junction of the
metal ends up in an increase within the carrier transport potency.

Fig:
Variation of vertical electric field as a function of the position along with
channel at metal 2.                The surface potential for
different drain voltage of the device structure along with the simulated
potential. The potential in the region under metal 1 increases but there is no
significant change in potential under metal 2.

Fig:
Variation of the surface potential as a function of the position along with
channel for metal 1.                The step changes in surface
potential of metal 2 indicates various values surface potential decreases then
it shifted towards the supply side . Then the drain current reduces by an order
when a thinner oxide is used, from 7nm to 5nm or 5nm to 2nm.

Fig:
Variation of the surface potential as a function of the position along with
channel for metal 2.                Drain current vs the generation
rate provides the enhanced carrier transport potency to supply. The rise within
the sub threshold drain current causes an increase in the sub threshold leakage
current and a decrease in the sub threshold swing .

Fig:
Variation of  the sub threshold drain
current IDS as a function of gate source voltage for metal 1.                The lower sub threshold  leakage for a thinner oxide thickness the
drain current reduces by order of 7nm to 5nm. This may attribute to greater
gate control and lower in oxide thickness.

Fig:
Variation of the sub threshold drain current IDS as a function of
the gate to source voltage for metal 2. V.
CONCLUSIONThe result of the proposed method accurately fit
between the measured I-V characteristics and simulation output. In this project
parabolic approximation technique used for OFET architecture in which the
structure has been analyzed and the performance improvements over different
parameter are discussed. The analytical model is based on two-dimensional
Poisson’s equation which is solved by using parabolic approximation. The
analytical  expression for surface
potential , vertical electric field have been calculated. Based on the
generation rate and electric field , we obtained the IDS-VGs
characteristics. From the presented results, it can be concluded that the
structure provides wide range of benefits to the OFET performance. The result
clearly demonstrate the excellent immunity against short channel effect offered
by the structure while decreasing channel length.